1. Field of the Invention
The present invention relates to a memory having a synchronous bank memory architecture.
2. Description of Prior Art
Synchronous multi-port memories can process read/write instructions in parallel. A multi-port memory has problems on area efficiency and arbitration for access conflicts. A multi-port bank memory has many 1-port memories with 1-port memory cells, referred to as banks, connected to the ports. Because 1-port cells are used, an area occupied by the memory can be decreased if compared with a conventional memory with N-port cells. Two architectures, that is, crossbar memory architecture and hierarchical memory architecture (HMA), are developed for a multi-port bank memory. In the crossbar multi-port memory, crossbar switches are provided between banks and ports. An HMA multi-port memory has a transition circuit between a port and N ports provided in each bank, row and column selectors for accessing one of the banks arranged in a matrix, and a central conflict management circuit is operated in parallel to the row and column selectors (for example, refer to H. J. Mattausch, Koji Kishi and Takayuki Gyohten, “Area-efficient multi-port SRAMs for on-chip data-storage with high random-access bandwidth and large storage capacity,” IEICE Transactions on Electronics, Vol. E84-C, No. 3, p. 410, 2001, and H. J. Mattausch, “Hierarchical architecture for area-efficient integrated N-port memories with latency-free multi-gigabit per second access bandwidth,” IEE Electronics Letters, Vol. 35, No. 17, pp. 1441–1443, 1999).
In a synchronous multi-port bank memory, in order to minimize access time, bit lines are precharged to a suitable voltage, and a sense amplifier is used conventionally. Memory access and the precharging of the bit lines are performed at different clock phases. For example, as shown in FIG. 1(a), the memory access is performed while clock signal ck=“1”, and the precharging is performed while clock ck=“0”. Therefore, a clock cycle time for the memory access (or memory access cycle time) consists of a sum of the precharging time and the memory access time, so that the clock cycle time becomes longer than the actual access time. However, in principle, it is desirable that the memory access cycle time is shortened to the memory access time.